Your roadmap · आपका रोडमैप
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Admission & first meetingप्रवेश और पहली मुलाकातEnquire at your nearest NDSS centre, meet the teacher, fix the batch time and get your study material.
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Part 1 of the syllabusपाठ्यक्रम भाग 1Unit-wise coaching with notes and doubt classes.
Unit 1: Introduction to VLSI DesignUnit 2: MOS Transistor and CMOS TechnologyUnit 3: CMOS Logic Circuits and Layout
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Part 2 of the syllabusपाठ्यक्रम भाग 2Unit-wise coaching with notes and doubt classes.
Unit 4: HDL Basics (Verilog)Unit 5: Programmable Logic Devices and FPGA
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Unit tests & assignmentsयूनिट टेस्टRegular tests in the university / board pattern.
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Semester 6 exam (university / board)विश्वविद्यालय / बोर्ड परीक्षाPrevious papers and full revision before the exam.
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Online tests & resultऑनलाइन टेस्ट और रिज़ल्टTake the tests online; your marks and result show in your student login and at the centre.
सिलेबस · पाठ्यक्रम
1 subject · 5 chapters · 25 topics
01Unit 1: Introduction to VLSI Design
5 टॉपिक+
- Evolution: SSI, MSI, LSI, VLSI
- Moore's law
- Design styles: full custom, standard cell, gate array, FPGA
- VLSI design flow and Y-chart
- ASIC vs FPGA
02Unit 2: MOS Transistor and CMOS Technology
6 टॉपिक+
- NMOS and PMOS transistors, threshold voltage
- CMOS inverter and transfer characteristic
- Noise margin
- Static and dynamic power dissipation
- Fabrication: oxidation, photolithography, diffusion, ion implantation, metallisation
- n-well CMOS process
03Unit 3: CMOS Logic Circuits and Layout
5 टॉपिक+
- CMOS NAND and NOR gates
- Complex gates
- Transmission gate
- Stick diagrams
- Lambda-based design rules and layout
04Unit 4: HDL Basics (Verilog)
5 टॉपिक+
- Verilog module, ports and data types (wire, reg)
- Gate level modelling
- Dataflow modelling with assign
- Behavioural modelling with always
- Test bench, simulation and synthesis
05Unit 5: Programmable Logic Devices and FPGA
4 टॉपिक+
- PROM, PLA and PAL
- CPLD
- FPGA architecture: CLB, LUT, IOB, interconnect
- FPGA design flow and tools
About this course
आप यह कर पाएँगे
- Explain the evolution of ICs, Moore's law, design styles and the VLSI design flow
- Explain MOS transistor operation, the CMOS inverter and CMOS power dissipation
- Outline CMOS fabrication steps (n-well process)
- Draw CMOS NAND, NOR and transmission gate circuits, stick diagrams and apply lambda rules
- Write simple Verilog models in gate, dataflow and behavioural styles with a test bench
- Compare PLA, PAL, CPLD and FPGA and describe the FPGA design flow
यह किसके लिए है
- Diploma Electronics Engineering students of Semester 6 (BTEUP)
- Polytechnic students of other boards studying the same subject who want unit-wise coaching
आपको क्या चाहिए
- Digital Electronics and Electronic Devices of earlier semesters
Online tests & result
Practice and unit tests online; marks and result show in your student login and at the centre.
Student login →
सवाल
Which syllabus does the VLSI Design course follow?
It follows the BTEUP (Board of Technical Education, Uttar Pradesh) diploma syllabus for VLSI Design (Electronics Engineering, Semester 6). If your own board's or institute's syllabus differs, the centre follows your own syllabus.
Will this help in the semester examination?
Yes. Teaching is unit-wise as per the BTEUP scheme, with previous-year question practice, MCQ tests and doubt sessions before the semester exam.
Which software is used for Verilog?
Free simulators such as Icarus Verilog / EDA Playground, and Xilinx Vivado or Intel Quartus for FPGA flow where available.
