Your roadmap · आपका रोडमैप
- 1
Admission & first meetingप्रवेश और पहली मुलाकातEnquire at your nearest NDSS centre, meet the teacher, fix the batch time and get your study material.
- 2
Work planकार्य योजनाStep by step with your guide / trainer.
Combinational Circuits on KitSequential Circuits on KitVerilog: Combinational DesignVerilog: Sequential Design and FPGA
- 3
File, report & vivaफ़ाइल, रिपोर्ट और वाइवाPractical file / report checked, mock viva before the final one.
- 4
Online tests & resultऑनलाइन टेस्ट और रिज़ल्टTake the tests online; your marks and result show in your student login and at the centre.
सिलेबस · पाठ्यक्रम
1 subject · 4 chapters · 16 topics
01Combinational Circuits on Kit
5 टॉपिक+
- Verification of gates and universal gates
- Half and full adder / subtractor
- Multiplexer and demultiplexer
- Decoder and encoder
- Magnitude comparator and code converters
02Sequential Circuits on Kit
4 टॉपिक+
- Verification of flip-flops
- Shift registers: SISO, SIPO, PISO, PIPO
- Ripple and synchronous counters
- Decade counter and ring / Johnson counter
03Verilog: Combinational Design
4 टॉपिक+
- Simulation tool flow
- Gate-level and dataflow adders
- Multiplexer and decoder in behavioural style
- Writing test benches
04Verilog: Sequential Design and FPGA
3 टॉपिक+
- Flip-flops and counters in Verilog
- Sequence detector FSM
- Synthesis, pin assignment and implementation on FPGA board
About this course
आप यह कर पाएँगे
- Verify logic gates and realise functions using universal gates
- Design and test adders, multiplexers, decoders and code converters on trainer kits
- Build flip-flop based shift registers and counters
- Write Verilog code and test benches for combinational and sequential circuits
- Implement a counter or FSM on an FPGA board
यह किसके लिए है
- B.Tech Electronics & Communication Engineering students of Semester 3 under AKTU
- Students who want guided practice before the internal and external lab examination and viva
आपको क्या चाहिए
- Digital System Design theory (studied alongside)
- Access to Xilinx Vivado / ModelSim or any Verilog simulator; a record file
Online tests & result
Practice and unit tests online; marks and result show in your student login and at the centre.
Student login →
सवाल
Which syllabus is followed?
The current AKTU (Dr. A.P.J. Abdul Kalam Technical University, Lucknow) B.Tech syllabus of Digital System Design Lab (Electronics & Communication Engineering, Semester 3). If your university or college follows a different syllabus, the centre teaches from your own university syllabus.
How is the lab assessed?
By the experiment performed, readings or output, the practical record file and a viva voce, as in the AKTU internal and external lab examination.
Do I need to maintain a record file?
Yes. The centre helps you write each experiment with aim, apparatus, theory, circuit diagram, observations, calculations, result and precautions.
