Your roadmap · आपका रोडमैप
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Admission & first meetingप्रवेश और पहली मुलाकातEnquire at your nearest NDSS centre, meet the teacher, fix the batch time and get your study material.
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Part 1 of the syllabusपाठ्यक्रम भाग 1Unit-wise coaching with notes and doubt classes.
Unit 1: Logic Minimisation and Combinational CircuitsUnit 2: Sequential CircuitsUnit 3: Finite State Machines
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Part 2 of the syllabusपाठ्यक्रम भाग 2Unit-wise coaching with notes and doubt classes.
Unit 4: Logic Families, Memories and PLDsUnit 5: Verilog HDL
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Unit tests & assignmentsयूनिट टेस्टRegular tests in the university / board pattern.
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Semester 3 exam (university / board)विश्वविद्यालय / बोर्ड परीक्षाPrevious papers and full revision before the exam.
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Online tests & resultऑनलाइन टेस्ट और रिज़ल्टTake the tests online; your marks and result show in your student login and at the centre.
Syllabus · पाठ्यक्रम
1 subject · 5 chapters · 29 topics
01Unit 1: Logic Minimisation and Combinational Circuits
7 topics+
- Number systems and codes
- Boolean algebra and canonical forms
- K-map up to five variables
- Quine-McCluskey method
- Adders, subtractors and carry look-ahead adder
- Multiplexers, demultiplexers, encoders and decoders
- Comparators and parity circuits
02Unit 2: Sequential Circuits
6 topics+
- Latches and flip-flops
- Flip-flop conversions and timing parameters
- Shift registers
- Ripple and synchronous counters
- Ring and Johnson counters
- Design of synchronous counters
03Unit 3: Finite State Machines
5 topics+
- Mealy and Moore models
- State diagram and state table
- State reduction and state assignment
- Sequence detector design
- ASM charts
04Unit 4: Logic Families, Memories and PLDs
5 topics+
- Characteristics: fan-out, noise margin, propagation delay, power
- TTL, ECL and CMOS families
- ROM and RAM
- PLA and PAL
- CPLD and FPGA (introduction)
05Unit 5: Verilog HDL
6 topics+
- Modules, ports and data types
- Operators
- Gate-level and dataflow modelling
- Behavioural modelling: always and initial blocks
- Blocking and non-blocking assignments
- Test benches and simulation
About this course
You will be able to
- Minimise logic functions with K-maps and the Quine-McCluskey method
- Design combinational circuits such as adders, comparators, multiplexers and decoders
- Design flip-flop based registers and synchronous and asynchronous counters
- Design Mealy and Moore finite state machines such as sequence detectors
- Compare TTL, ECL and CMOS logic families and explain memories and PLDs
- Write Verilog HDL code for combinational and sequential circuits
Who it is for
- B.Tech Electronics & Communication Engineering students of Semester 3 under AKTU
- Students preparing for AKTU examinations, GATE digital electronics and VLSI basics
What you need
- Basic Electronics of the first year and number systems
Online tests & result
Practice and unit tests online; marks and result show in your student login and at the centre.
Student login →
Questions
Which syllabus is followed?
The current AKTU (Dr. A.P.J. Abdul Kalam Technical University, Lucknow) B.Tech syllabus of Digital System Design (Electronics & Communication Engineering, Semester 3). If your university or college follows a different syllabus, the centre teaches from your own university syllabus.
How is the subject examined?
AKTU assesses it through sessional tests, assignments and attendance, and an end-semester university examination; the centre covers every unit with theory, derivations and numericals.
Are previous-year questions practised?
Yes. Unit-wise AKTU previous-year questions, short-answer questions and the test series are solved in class.
