Your roadmap · आपका रोडमैप
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Admission & first meetingप्रवेश और पहली मुलाकातEnquire at your nearest NDSS centre, meet the teacher, fix the batch time and get your study material.
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Part 1 of the syllabusपाठ्यक्रम भाग 1Unit-wise coaching with notes and doubt classes.
Unit 1: Introduction, Buses and Addressing ModesUnit 2: Arithmetic and Logic UnitUnit 3: Control Unit and Pipelining
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Part 2 of the syllabusपाठ्यक्रम भाग 2Unit-wise coaching with notes and doubt classes.
Unit 4: Memory OrganisationUnit 5: Input-Output Organisation
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Unit tests & assignmentsयूनिट टेस्टRegular tests in the university / board pattern.
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Semester 3 exam (university / board)विश्वविद्यालय / बोर्ड परीक्षाPrevious papers and full revision before the exam.
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Online tests & resultऑनलाइन टेस्ट और रिज़ल्टTake the tests online; your marks and result show in your student login and at the centre.
Syllabus · पाठ्यक्रम
1 subject · 5 chapters · 29 topics
01Unit 1: Introduction, Buses and Addressing Modes
6 topics+
- Functional units of a digital computer and their interconnection
- Buses, bus architecture, types of buses
- Bus arbitration: daisy chaining, polling, independent requests
- Register, bus and memory transfer (RTL)
- General register organisation and stack organisation
- Addressing modes
02Unit 2: Arithmetic and Logic Unit
6 topics+
- Look-ahead carry adders
- Signed operand multiplication and Booth's algorithm
- Array multiplier
- Division (restoring and non-restoring) and logic operations
- Floating point representation and IEEE 754
- Floating point arithmetic and ALU design
03Unit 3: Control Unit and Pipelining
6 topics+
- Instruction types and formats
- Instruction cycle, fetch and execute sub-cycles, micro-operations
- Program control, RISC and CISC
- Pipelining: basic concepts, data and instruction hazards
- Hardwired control
- Microprogrammed control: sequencing, next-address field, horizontal and vertical microprogramming
04Unit 4: Memory Organisation
5 topics+
- Memory hierarchy
- Semiconductor RAM, 2D and 2.5D organisation, ROM
- Cache memory: performance, mapping and replacement
- Auxiliary memory: magnetic disk, tape, optical disk
- Virtual memory concept and implementation
05Unit 5: Input-Output Organisation
6 topics+
- Peripheral devices, I/O interface and I/O ports
- Interrupts: hardware, types and exceptions
- Programmed I/O and interrupt-initiated I/O
- Direct Memory Access (DMA)
- I/O channels and processors
- Synchronous and asynchronous serial communication, standard interfaces
About this course
You will be able to
- Explain the functional units of a computer, bus structure and bus arbitration
- Use register transfer language, stack organisation and addressing modes
- Perform signed multiplication (Booth's algorithm), division and IEEE 754 floating point arithmetic
- Describe instruction cycle, hardwired and microprogrammed control, RISC and CISC
- Analyse pipeline performance and hazards
- Design memory organisation and calculate cache mapping fields and average access time
- Compare programmed I/O, interrupt-driven I/O and DMA
Who it is for
- B.Tech Computer Science & Engineering, Information Technology students of Semester 3 (AKTU)
- Students of other universities studying the same subject who want unit-wise coaching
What you need
- Digital electronics basics: number systems, logic gates, flip-flops
- Basic programming knowledge
Online tests & result
Practice and unit tests online; marks and result show in your student login and at the centre.
Student login →
Questions
Which syllabus does the Computer Organization and Architecture course follow?
It follows the AKTU (Dr. A.P.J. Abdul Kalam Technical University, Lucknow) B.Tech syllabus for Computer Organization and Architecture. If your own university's syllabus differs, the centre follows your university syllabus.
Will this help in the university examination?
Yes. Teaching is unit-wise as per the AKTU scheme, with previous-year question practice, MCQ tests and doubt sessions before the semester exam.
Are numericals covered?
Yes: Booth multiplication, IEEE 754 conversion, pipeline speed-up, cache mapping and average memory access time are practised in every batch.
